Reducing the impact of interference during programming

ABSTRACT

A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

This application is a continuation application of U.S. patentapplication Ser. No. 11/849,992, titled “REDUCING THE IMPACT OFINTERFERENCE DURING PROGRAMMING,” filed Sep. 4, 2007, which isincorporated herein by reference.

BACKGROUND

1. Field

The present invention relates to technology for non-volatile storage.

2. Description of the Related Art

Semiconductor memory has become more popular for use in variouselectronic devices. For example, non-volatile semiconductor memory isused in cellular telephones, digital cameras, personal digitalassistants, mobile computing devices, non-mobile computing devices andother devices. Electrical Erasable Programmable Read Only Memory(EEPROM) and flash memory are among the most popular non-volatilesemiconductor memories.

Both EEPROM and flash memory utilize a floating gate that is positionedabove and insulated from a channel region in a semiconductor substrate.The floating gate is positioned between the source and drain regions. Acontrol gate is provided over and insulated from the floating gate. Thethreshold voltage of the transistor is controlled by the amount ofcharge that is retained on the floating gate. That is, the minimumamount of voltage that must be applied to the control gate before thetransistor is turned on to permit conduction between its source anddrain is controlled by the level of charge on the floating gate. Thus, amemory cell (which can include one or more transistors) can beprogrammed and/or erased by changing the level of charge on a floatinggate in order to change the threshold voltage.

Each memory cell can store data (analog or digital). When storing onebit of digital data (referred to as a binary memory cell), possiblethreshold voltages of the memory cell are divided into two ranges whichare assigned logical data “1” and “0.” In one example of a NAND typeflash memory, the threshold voltage is negative after the memory cell iserased, and defined as logic “1.” After programming, the thresholdvoltage is positive and defined as logic “0.” When the threshold voltageis negative and a read is attempted by applying 0 volts to the controlgate, the memory cell will turn on to indicate logic one is beingstored. When the threshold voltage is positive and a read operation isattempted by applying 0 volts to the control gate, the memory cell willnot turn on, which indicates that logic zero is stored.

A memory cell can also store multiple levels of information (referred toas a multi-state memory cell). In the case of storing multiple levels ofdata, the range of possible threshold voltages is divided into thenumber of levels of data. For example, if four levels of information isstored, there will be four threshold voltage ranges assigned to the datavalues “11”, “10”, “01”, and “00.” In one example of a NAND type memory,the threshold voltage after an erase operation is negative and definedas “11.” Positive threshold voltages are used for the states of “10”,“01”, and “00.” If eight levels of information (or states) are stored ineach memory cell (e.g. for three bits of data), there will be eightthreshold voltage ranges assigned to the data values “000”, “001”,“010”, “011” “100”, “101”, “110” and “111.” The specific relationshipbetween the data programmed into the memory cell and the thresholdvoltage levels of the memory cell depends upon the data encoding schemeadopted for the memory cells. For example, U.S. Pat. No. 6,222,762 andU.S. Patent Application Publication No. 2004/0255090, both of which areincorporated herein by reference in their entirety, describe variousdata encoding schemes for multi-state flash memory cells. In oneembodiment, data values are assigned to the threshold voltage rangesusing a Gray code assignment so that if the threshold voltage of afloating gate erroneously shifts to its neighboring physical state, onlyone bit will be affected. In some embodiments, the data encoding schemecan be changed for different word lines, the data encoding scheme can bechanged over time, or the data bits for random word lines may beinverted to reduce data pattern sensitivity and even wear on the memorycells. Different encoding schemes can be used.

When programming an EEPROM or flash memory device, such as a NAND flashmemory device, typically a program voltage is applied to the controlgate and the bit line is grounded. Electrons from the channel areinjected into the floating gate. When electrons accumulate in thefloating gate, the floating gate becomes negatively charged and thethreshold voltage of the memory cell is raised so that the memory cellis in a programmed state. More information about programming can befound in U.S. Pat. No. 6,859,397, titled “Source Side Self BoostingTechnique For Non-Volatile Memory,” and in U.S. Patent ApplicationPublication 2005/0024939, titled “Detecting Over Programmed Memory,”both of which are incorporated herein by reference in their entirety. Inmany devices, the program voltage applied to the control gate during aprogram operation is applied as a series of pulses in which themagnitude of the pulses is increased by a predetermined step size foreach successive pulse.

Many non-volatile storage systems include an array of memory cellsarranged in columns and rows. Control lines (e.g., word lines, bitlines, or other types of control lines) connect to the various rows andcolumns. In one example, word lines are used to access rows of memorycells while bit lines are used to access columns of memory cell. In thisarrangement, the series of pulses of the program voltage are applied toa selected word line that is connected to a set of selected memorycells. Each of the selected memory cells receiving the pulsespotentially has its threshold voltage raised in response thereto. As thememory cells reach their target threshold voltage, they are locked outfrom further programming. It has been observed that as memory cellsbecome locked out, they interfere with the expected programming rate oftheir neighbor memory cells. This effect can cause the neighbor memorycells to overshoot their intended target threshold voltage and,therefore, become over-programmed. In some cases, an over-programmedmemory cell will cause an error when being read.

SUMMARY

Technology is described herein that reduces the impact of interferencebetween neighboring memory cells during programming.

One embodiment includes performing programming on a first group ofnon-volatile storage elements at a first time, performing programming ona second group of non-volatile storage elements at a second timedifferent from the first time, and verifying the first group ofnon-volatile storage elements and the second group of non-volatilestorage elements together.

One embodiment includes applying multiple programming pulses to a set ofnon-volatile storage elements including programming a first subset ofthe non-volatile storage elements with a first programming pulse withoutintentionally programming a second subset of the non-volatile storageelements and programming the second subset of the non-volatile storageelements with a second programming pulse without intentionallyprogramming the first subset of the non-volatile storage elements. Theprocess further comprises performing a verification process for the setof non-volatile storage elements subsequent to applying the firstprogramming pulse and the second programming pulse. The verificationprocess includes verifying whether the first subset of non-volatilestorage elements have reached one or more targets in response to thefirst programming pulse and verifying whether the second subset ofnon-volatile storage elements have reached one or more targets inresponse to the second programming pulse.

One embodiment includes, before a first trigger, programming togetherand verifying together a first group of non-volatile storage elementsand a second group of non-volatile storage elements. After the firsttrigger, the first group of non-volatile storage elements is programmedseparately from the second group of non-volatile storage elements andthe first group of non-volatile storage elements is verified togetherwith the second group of non-volatile storage elements.

One embodiment includes, before detecting a first condition, performinga set of one or more programming cycles that each include using a firstpulse to program a first subset of non-volatile storage elements andseparately using a second pulse to program a second subset ofnon-volatile storage elements. The one or more programming cyclesinclude verifying the first subset of non-volatile storage elements andthe second subset of non-volatile storage elements together. Afterdetecting the first condition, a group of one or more program cycles areperformed that each include using one pulse to program the first subsetof non-volatile storage elements and the second subset of the group ofnon-volatile storage elements together. The group of one or more programcycles includes verifying the first subset of non-volatile storageelements and the second subset of non-volatile storage elementstogether.

One embodiment comprises a plurality of non-volatile storage elements(including a first group of non-volatile storage elements and a secondgroup of non-volatile storage elements) and one or more managingcircuits in communication with the non-volatile storage elements. Theone or more managing circuits program the first group of non-volatilestorage elements separately from programming the second group ofnon-volatile storage elements. The one or more managing circuits verifythe first group of non-volatile storage elements together with verifyingthe second group of non-volatile storage elements.

One embodiment comprises a plurality of non-volatile storage elements(including a first group of non-volatile storage elements and a secondgroup of non-volatile storage elements) and one or more managingcircuits in communication with the non-volatile storage elements. Beforea trigger, the one or more managing circuits perform a first set of oneor more program cycles and after the trigger the one or more managingcircuits perform a second set of one or more program cycles. The firstset of one or more program cycles each use one pulse to program thegroup of non-volatile storage elements together. The first set of one ormore program cycles each verify the group of non-volatile storageelements together. The second set of one or more program cycles each usea first pulse to program the first subset of non-volatile storageelements and separately use a second pulse to program the second subsetof non-volatile storage elements. The second set of one or more programcycles each verify the group of non-volatile storage elements together.

One embodiment comprises a first group of non-volatile storage elements,a second group of non-volatile storage elements, and one or moremanaging circuits in communication with the first group of non-volatilestorage elements and the second group of non-volatile storage elements.Before a condition, the one or more managing circuits program the firstgroup of non-volatile storage elements separately from the second groupof non-volatile storage elements and verify the first group ofnon-volatile storage elements together with the second group ofnon-volatile storage elements. After the condition the one or moremanaging circuits program and verify the first group of non-volatilestorage elements and the second group of non-volatile storage elementstogether.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view of a NAND string.

FIG. 2 is an equivalent circuit diagram of the NAND string.

FIG. 3 is a block diagram of a non-volatile memory system.

FIG. 4 is a block diagram depicting one embodiment of a memory array.

FIG. 5 is a block diagram depicting one embodiment of a sense block.

FIG. 6 depicts an example set of threshold voltage distributions anddescribes a process for programming non-volatile memory.

FIGS. 7A-I show various threshold voltage distributions and describe aprocess for programming non-volatile memory.

FIG. 8 is a table depicting one example of an order of programmingnon-volatile memory.

FIG. 9 depicts a flow chart describing one embodiment of a process forprogramming non-volatile memory.

FIG. 10 depicts a flow chart describing one embodiment of a process forprogramming non-volatile memory elements.

FIGS. 11A-C depict portions of two example neighboring memory cells.

FIG. 12 depicts a set of program pulses.

FIG. 13 depicts a set of program pulses.

FIG. 14 depicts a set of program pulses and verify pulses.

FIG. 15 depicts a set of program pulses and verify pulses.

FIG. 16 depicts example waveforms.

FIG. 17 is a flow chart describing one embodiment of a process fordetermining whether a condition exists.

FIG. 18 is a block diagram of one embodiment of a circuit thatdetermines whether a condition exists.

FIG. 19 is a flow chart describing one embodiment of a process fordetermining whether a condition exists.

FIG. 20 is a block diagram of one embodiment of a circuit thatdetermines whether a condition exists.

FIG. 21 is a flow chart describing one embodiment of a process fordetermining a trigger point to change the programming process.

FIG. 22 is a flow chart describing one embodiment of a process fordetermining a trigger point to change the programming process.

FIG. 23 is a flow chart describing one embodiment of a process fordetermining a trigger point to change the programming process.

FIG. 24 is a flow chart describing one embodiment of a process fordynamically adjusting a trigger voltage.

FIG. 25 is a block diagram illustrating some of the components thatimplement the process of FIG. 24.

FIG. 26 is a flow chart describing one embodiment of a process fordynamically adjusting a trigger voltage.

FIG. 27 is a block diagram illustrating some of the components thatimplement the process of FIG. 26.

DETAILED DESCRIPTION

One example of a flash memory system uses the NAND structure, whichincludes arranging multiple transistors in series, sandwiched betweentwo select gates. The transistors in series and the select gates arereferred to as a NAND string. FIG. 1 is a top view showing one NANDstring. FIG. 2 is an equivalent circuit thereof. The NAND stringdepicted in FIGS. 1 and 2 includes four transistors 100, 102, 104 and106 in series and sandwiched between a first (or drain side) select gate120 and a second (or source side) select gate 122. Select gate 120connects the NAND string to a bit line via bit line contact 126. Selectgate 122 connects the NAND string to source line 128. Select gate 120 iscontrolled by applying the appropriate voltages to select line SGD.Select gate 122 is controlled by applying the appropriate voltages toselect line SGS. Each of the transistors 100, 102, 104 and 106 has acontrol gate and a floating gate. For example, transistor 100 hascontrol gate 100CG and floating gate 100FG. Transistor 102 includescontrol gate 102CG and a floating gate 102FG. Transistor 104 includescontrol gate 104CG and floating gate 104FG. Transistor 106 includes acontrol gate 106CG and a floating gate 106FG. Control gate 100CG isconnected to word line WL3, control gate 102CG is connected to word lineWL2, control gate 104CG is connected to word line WL1, and control gate106CG is connected to word line WL0.

Note that although FIGS. 1 and 2 show four memory cells in the NANDstring, the use of four memory cells is only provided as an example. ANAND string can have less than four memory cells or more than fourmemory cells. For example, some NAND strings will include eight memorycells, 16 memory cells, 32 memory cells, 64 memory cells, 128 memorycells, etc. The discussion herein is not limited to any particularnumber of memory cells in a NAND string.

A typical architecture for a flash memory system using a NAND structurewill include several NAND strings. Each NAND string is connected to thesource line by its source select gate controlled by select line SGS andconnected to its associated bit line by its drain select gate controlledby select line SGD. Each bit line and the respective NAND string(s) thatare connected to that bit line via a bit line contact comprise thecolumns of the array of memory cells. Bit lines are shared with multipleNAND strings. Typically, the bit line runs on top of the NAND strings ina direction perpendicular to the word lines and is connected to one ormore sense amplifiers.

Relevant examples of NAND type flash memories and their operation areprovided in the following U.S. patents/patent applications, all of whichare incorporated herein by reference: U.S. Pat. No. 5,570,315; U.S. Pat.No. 5,774,397; U.S. Pat. No. 6,046,935; U.S. Pat. No. 6,456,528; andU.S. Pat. Publication No. US2003/0002348. The discussion herein can alsoapply to other types of flash memory in addition to NAND, as well asother types of non-volatile memory.

Other types of non-volatile storage devices, in addition to NAND flashmemory, can also be used. For example, non-volatile memory devices arealso manufactured from memory cells that use a dielectric layer forstoring charge. Instead of the conductive floating gate elementsdescribed earlier, a dielectric layer is used. Such memory devicesutilizing dielectric storage element have been described by Eitan etal., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,”IEEE Electron Device Letters, vol. 21, no. 11, November 2000, pp.543-545. An ONO dielectric layer extends across the channel betweensource and drain diffusions. The charge for one data bit is localized inthe dielectric layer adjacent to the drain, and the charge for the otherdata bit is localized in the dielectric layer adjacent to the source.For example, U.S. Pat. Nos. 5,768,192 and 6,011,725 disclose anonvolatile memory cell having a trapping dielectric sandwiched betweentwo silicon dioxide layers. Multi-state data storage is implemented byseparately reading the binary states of the spatially separated chargestorage regions within the dielectric. Other types of non-volatilestorage can also be used.

FIG. 3 illustrates a memory device 210 having read/write circuits forreading and programming a page (or other unit) of memory cells (e.g.,NAND multi-state flash memory) in parallel. Memory device 210 mayinclude one or more memory die or chips 212. Memory die 212 includes anarray (two-dimensional or three dimensional) of memory cells 200,control circuitry 220, and read/write circuits 230A and 230B. In oneembodiment, access to the memory array 200 by the various peripheralcircuits is implemented in a symmetric fashion, on opposite sides of thearray, so that the densities of access lines and circuitry on each sideare reduced by half. The read/write circuits 230A and 230B includemultiple sense blocks 300 which allow a page of memory cells to be reador programmed in parallel. The memory array 200 is addressable by wordlines via row decoders 240A and 240B and by bit lines via columndecoders 242A and 242B. Word lines and bit lines are examples of controllines. In a typical embodiment, a controller 244 is included in the samememory device 210 (e.g., a removable storage card or package) as the oneor more memory die 212. Commands and data are transferred between thehost and controller 244 via lines 232 and between the controller and theone or more memory die 212 via lines 234.

Control circuitry 220 cooperates with the read/write circuits 230A and230B to perform memory operations on the memory array 200. The controlcircuitry 220 includes a state machine 222, an on-chip address decoder224 and a power control module 226. The state machine 222 provideschip-level control of memory operations. The on-chip address decoder 224provides an address interface between that used by the host or a memorycontroller to the hardware address used by the decoders 240A, 240B,242A, and 242B. The power control module 226 controls the power andvoltages supplied to the word lines and bit lines during memoryoperations. In one embodiment, power control module 226 includes one ormore charge pumps that can create voltages larger than the supplyvoltage.

In one embodiment, one or any combination of control circuitry 220,power control circuit 226, decoder circuit 224, state machine circuit222, decoder circuit 242A, decoder circuit 242B, decoder circuit 240A,decoder circuit 240B, read/write circuits 230A, read/write circuits230B, and/or controller 244 can be referred to as one or more managingcircuits. The one or more managing circuits perform the processesdescribed herein.

FIG. 4 depicts an exemplary structure of memory cell array 200. In oneembodiment, the array of memory cells is divided into a large number ofblocks (e.g., blocks 0-1023, or another amount) of memory cells. As iscommon for flash EEPROM systems, the block is the unit of erase. Thatis, each block contains the minimum number of memory cells that areerased together. Other units of eras can also be used.

A block contains a set of NAND stings which are accessed via bit lines(e.g., bit lines BL0-BL69623) and word lines (WL0, WL1, WL2, WL3). FIG.4 shows four memory cells connected in series to form a NAND string.Although four cells are shown to be included in each NAND string, moreor less than four can be used (e.g., 16, 32, 64, 128 or another numberor memory cells can be on a NAND string). One terminal of the NANDstring is connected to a corresponding bit line via a drain select gate(connected to select gate drain line SGD), and another terminal isconnected to the source line via a source select gate (connected toselect gate source line SGS).

Each block is typically divided into a number of pages. In oneembodiment, a page is a unit of programming. Other units of programmingcan also be used. One or more pages of data are typically stored in onerow of memory cells. For example, one or more pages of data may bestored in memory cells connected to a common word line. A page can storeone or more sectors. A sector includes user data and overhead data (alsocalled system data). Overhead data typically includes header informationand Error Correction Codes (ECC) that have been calculated from the userdata of the sector. The controller (or other component) calculates theECC when data is being programmed into the array, and also checks itwhen data is being read from the array. Alternatively, the ECCs and/orother overhead data are stored in different pages, or even differentblocks, than the user data to which they pertain. A sector of user datais typically 512 bytes, corresponding to the size of a sector inmagnetic disk drives. A large number of pages form a block, anywherefrom 8 pages, for example, up to 32, 64, 128 or more pages. Differentsized blocks, pages and sectors can also be used.

FIG. 5 is a block diagram of an individual sense block 300 partitionedinto a core portion, referred to as a sense module 480, and a commonportion 490. In one embodiment, there will be a separate sense module480 for each bit line and one common portion 490 for a set of multiplesense modules 480. In one example, a sense block will include one commonportion 490 and eight sense modules 480. Each of the sense modules in agroup will communicate with the associated common portion via a data bus472. One example can be found in U.S. Patent Application Publication2006/0140007, which is incorporated herein by reference in its entirety.

Sense module 480 comprises sense circuitry 470 that determines whether aconduction current in a connected bit line is above or below apredetermined level. In some embodiments, sense module 480 includes acircuit commonly referred to as a sense amplifier. Sense module 480 alsoincludes a bit line latch 482 that is used to set a voltage condition onthe connected bit line. For example, a predetermined state latched inbit line latch 482 will result in the connected bit line being pulled toa state designating program inhibit (e.g., Vdd).

Common portion 490 comprises a processor 492, a set of data latches 494and an I/O Interface 496 coupled between the set of data latches 494 anddata bus 420. Processor 492 performs computations. For example, one ofits functions is to determine the data stored in the sensed memory celland store the determined data in the set of data latches. The set ofdata latches 494 is used to store data bits determined by processor 492during a read operation. It is also used to store data bits importedfrom the data bus 420 during a program operation. The imported data bitsrepresent write data meant to be programmed into the memory. I/Ointerface 496 provides an interface between data latches 494 and thedata bus 420.

During read or sensing, the operation of the system is under the controlof state machine 222 that controls (using power control 226) the supplyof different control gate voltages to the addressed memory cell(s). Asit steps through the various predefined control gate voltagescorresponding to the various memory states supported by the memory, thesense module 480 may trip at one of these voltages and an output will beprovided from sense module 480 to processor 492 via bus 472. At thatpoint, processor 492 determines the resultant memory state byconsideration of the tripping event(s) of the sense module and theinformation about the applied control gate voltage from the statemachine via input lines 493. It then computes a binary encoding for thememory state and stores the resultant data bits into data latches 494.In another embodiment of the core portion, bit line latch 482 servesdouble duty, both as a latch for latching the output of the sense module480 and also as a bit line latch as described above.

It is anticipated that some implementations will include multipleprocessors 492. In one embodiment, each processor 492 will include anoutput line (not depicted in FIG. 5) such that each of the output linesis wired-OR'd together. In some embodiments, the output lines areinverted prior to being connected to the wired-OR line. Thisconfiguration enables a quick determination during the programverification process of when the programming process has completedbecause the state machine receiving the wired-OR line can determine whenall bits being programmed have reached the desired level. For example,when each bit has reached its desired level, a logic zero for that bitwill be sent to the wired-OR line (or a data one is inverted). When allbits output a data 0 (or a data one inverted), then the state machineknows to terminate the programming process. In embodiments where eachprocessor communicates with eight sense modules, the state machine may(in some embodiments) need to read the wired-OR line eight times, orlogic is added to processor 492 to accumulate the results of theassociated bit lines such that the state machine need only read thewired-OR line one time.

Data latch stack 494 contains a stack of data latches corresponding tothe sense module. In one embodiment, there are three (or four or anothernumber) data latches per sense module 480. In one embodiment, thelatches are each one bit.

During program or verify, the data to be programmed is stored in the setof data latches 494 from the data bus 420. During the verify process,Processor 492 monitors the verified memory state relative to the desiredmemory state. When the two are in agreement, processor 492 sets the bitline latch 482 so as to cause the bit line to be pulled to a statedesignating program inhibit. This inhibits the memory cell coupled tothe bit line from further programming even if it is subjected toprogramming pulses on its control gate. In other embodiments theprocessor initially loads the bit line latch 482 and the sense circuitrysets it to an inhibit value during the verify process.

In some implementations (but not required), the data latches areimplemented as a shift register so that the parallel data stored thereinis converted to serial data for data bus 420, and vice versa. In onepreferred embodiment, all the data latches corresponding to theread/write block of m memory cells can be linked together to form ablock shift register so that a block of data can be input or output byserial transfer. In particular, the bank of read/write modules isadapted so that each of its set of data latches will shift data in to orout of the data bus in sequence as if they are part of a shift registerfor the entire read/write block.

Additional information about the sensing operations and sense amplifierscan be found in (1) United States Patent Application Pub. No.2004/0057287, “Non-Volatile Memory And Method With Reduced Source LineBias Errors,” published on Mar. 25, 2004; (2) United States PatentApplication Pub No. 2004/0109357, “Non-Volatile Memory And Method withImproved Sensing,” published on Jun. 10, 2004; (3) U.S. PatentApplication Pub. No. 20050169082; (4) U.S. Patent Publication2006/0221692, titled “Compensating for Coupling During Read Operationsof Non-Volatile Memory,” Inventor Jian Chen, filed on Apr. 5, 2005; and(5) U.S. patent application Ser. No. 11/321,953, titled “Reference SenseAmplifier For Non-Volatile Memory, Inventors Siu Lung Chan andRaul-Adrian Cernea, filed on Dec. 28, 2005. All five of the immediatelyabove-listed patent documents are incorporated herein by reference intheir entirety.

At the end of a successful programming process (with verification), thethreshold voltages of the memory cells should be within one or moredistributions of threshold voltages for programmed memory cells orwithin a distribution of threshold voltages for erased memory cells, asappropriate. FIG. 6 illustrates example threshold voltage distributions(or data states) for the memory cell array when each memory cell storesthree bits of data. Other embodiment, however, may use more or less thanthree bits of data per memory cell (e.g., such as four or more bits ofdata per memory cell).

In the example of FIG. 6, each memory cell stores three bits of data;therefore, there are eight valid data states S0-S7. In one embodiment,data state S0 is below 0 volts and data states S1-S7 are above 0 volts.In other embodiments, all eight data states are above 0 volts, or otherarrangements can be implemented. In one embodiment, the thresholdvoltage distribution S0 is wider than distributions S1-S7.

Each data state corresponds to a unique value for the three bits storedin the memory cell. In one embodiment, S0=111, S1=110, S2=101, S3=100,S4=011, S5=010, S6=001 and S7=000. Other mapping of data to states S0-S7can also be used. In one embodiment, all of the bits of data stored in amemory cell are stored in the same logical page. In other embodiments,each bit of data stored in a memory cell correspond to different pages.Thus, a memory cell storing three bits of data would include data in afirst page, a second page and a third page. In some embodiments, all ofthe memory cells connected to the same word line would store data in thesame three pages of data. In some embodiments, the memory cellsconnected to a word line can be grouped in to different sets of pages(e.g., by odd and even bit lines, or by other arrangements).

In some prior art devices, the memory cells will be erased to state S0.From state S0, the memory cells can be programmed to any of statesS1-S7. In one embodiment, known as full sequence programming, memorycells can be programmed from the erased state S0 directly to any of theprogrammed states S1-S7. For example, a population of memory cells to beprogrammed may first be erased so that all memory cells in thepopulation are in erased state S0. While some memory cells are beingprogrammed from state S0 to state S1, other memory cells are beingprogrammed from state S0 to state S2, state S0 to state S3, state S0 tostate S4, state S0 to state S5, state S0 to state S6, and state S0 tostate S7. Full sequence programming is graphically depicted by the sevencurved arrows of FIG. 6.

FIGS. 7A-7I disclose another process for programming non-volatile memorythat reduces the effect of floating gate to floating gate coupling by,for any particular memory cell, writing to that particular memory cellwith respect to a particular page subsequent to writing to adjacentmemory cells for previous pages. The process of FIGS. 7A-7I is a threestep programming process. Prior to the first step, the memory cells willbe erased so that they are in the erase threshold distribution of stateS0.

The process of FIGS. 7A-7I assumes that each memory cell stores threebits of data, with each bit being in a different page. The first bit ofdata (the leftmost bit) is associated with the first page. The middlebit is associated with the second page. The rightmost bit is associatedwith the third page. The correlation of data states to data is asfollows: S0=111, S1=110, S2=101, S3=100, S4=011, S5=010, S6=001 andS7=000. However, other embodiments can use other data encoding schemes.

When programming the first page (as described in FIG. 7A), if the bit isto be data “1” then the memory cell will stay in state S0 (thresholdvoltage distribution 502). If the bit is to be data “0” then the memorycell is programmed to state S4 (threshold voltage distribution 504).After adjacent memory cells are programmed, capacitive coupling betweenadjacent floating gates may cause the state S4 to widen as depicted inFIG. 7B. State S0 may also widen, but there is sufficient margin betweenS0 and S1 to ignore the effect. More information about capacitivecoupling between adjacent floating gates can be found in U.S. Pat. No.5,867,429 and U.S. Pat. No. 6,657,891, both of which are incorporatedherein by reference in their entirety.

When programming the second page (see FIG. 7C), if the memory cell is instate S0 and the second page bit is data “1” then the memory cell staysin state S0. In some embodiments, the programming process for the secondpage will tighten threshold voltage distribution 501 to a new S0. If thememory cell was in state S0 and the data to be written to the secondpage is “0”, then the memory cell is moved to state S2 (thresholdvoltage distribution 506). State S2 has a verify point (lowest voltage)of C*. If the memory cell was in state S4 and the data to be written tothe memory cell is “1” then the memory cell remains in S4. However,state S4 is tightened by moving the memory cells from threshold voltagedistribution 504 to threshold voltage distribution 508 for state S4, asdepicted in FIG. 7C. Threshold voltage distribution 508 has a verifypoint of E* (as compared to E** of threshold voltage distribution 504).If the memory cell is in state S4 and the data to be written to thesecond page is a “0” then the memory cell has its threshold voltagemoved to state S6 (threshold voltage distribution 510), with a verifypoint of G*.

After the adjacent memory cells are programmed, the states S2, S4 and S6are widened due to the floating gate to floating gate coupling, asdepicted by threshold voltages distributions 506, 508 and 510 of FIG.7D. In some cases, state S0 may also widen.

FIGS. 7E, 7F, 7G and 7H depict the programming of the third page. Whileone graph can be used to show the programming, the process is depictedin four graphs for visibility reasons. After the second page has beenprogrammed, the memory cells are either in states S0, S2, S4 or S6. FIG.7E shows the memory cell that is in state S0 being programmed for thethird page. FIG. 7F shows the memory cell that is state S2 beingprogrammed for the third page. FIG. 7G shows the memory cell that is instate S4 being programmed for the third page. FIG. 7H shows the memorycell that is in state S6 being programmed for the third page. FIG. 7Ishows the threshold voltage distributions after the processes of FIGS.7E, 7F, 7G and 7H have been performed on the population of memory cells(concurrently or serially).

If the memory cell is in state S0 and the third page data is “1” thenthe memory cell remains at state S0. If the data for the third page is“0” then the threshold voltage for the memory cell is raised to be instate 51, with a verify point of B (see FIG. 7E).

If the memory cells in state S2 and the data to be written in the thirdpage is “1”, then the memory cell will remain in state S2 (see FIG. 7F).However, some programming will be performed to tighten the thresholddistribution 506 to a new state S2 with a verify point of C volts. Ifthe data to be written to the third page is “0,” then the memory cellwill be programmed to state S3, with a verify point of D volts.

If the memory cell is in state S4 and the data to be written to thethird page is “1” then the memory cell will remain in state S4 (see FIG.7G). However, some programming will be performed so that thresholdvoltage distribution 508 will be tightened to new state S4 with a verifypoint of E. If the memory cell is in state S4 and the data to be writtento the third page is “0” then the memory cell will have its thresholdvoltage raised to be in state S5, with a verify point of F.

If the memory cell is in state S6 and the data to be written to thethird page is “1” then the memory cell will remain in state S6 (see FIG.7H). However, there will be some programming so that the thresholdvoltage distribution 510 is tightened to be in new state S6, with averify point at G. If the third page data is “0” then the memory cellwill have its threshold voltage programmed to state S7, with a verifypoint at H. At the conclusion of the programming of the third page, thememory cell will be in one of the eight states depicted in FIG. 7I.

FIG. 8 depicts one example of an order for programming the pages of aset or memory cells. The table provides the order for programming withrespect to the four word lines (WL0, WL1, WL2 and WL3) of FIG. 4;however, the table can be adapted to accommodate more or less than fourword lines. The first page of the memory cells connected to WL0 areprogrammed, followed by the programming of the first page of the memorycells connected to WL1, followed by the programming of the second pageof the memory cells connected to WL0, followed by the programming of thefirst page of the memory cells connected to WL2, followed by theprogramming of the second page of the memory cells connected to WL1,etc.

FIG. 9 is a flow chart describing a programming process for programmingmemory cells connected to a selected word line. In one embodiment, theprocess of FIG. 9 is used to program a block of memory cells. In oneimplementation of the process of FIG. 9, memory cells are pre-programmedin order to maintain even wear on the memory cells (step 550). In oneembodiment, the memory cells are preprogrammed to state 7, a randompattern, or any other pattern. In some implementations, pre-programmingneed not be performed.

In step 552, memory cells are erased (in blocks or other units) prior toprogramming. Memory cells are erased in one embodiment by raising thep-well to an erase voltage (e.g., 20 volts) for a sufficient period oftime and grounding the word lines of a selected block while the sourceand bit lines are floating. Due to capacitive coupling, the unselectedword lines, bit lines, select lines, and the common source line are alsoraised to a significant fraction of the erase voltage. A strong electricfield is thus applied to the tunnel oxide layers of selected memorycells and the selected memory cells are erased as electrons of thefloating gates are emitted to the substrate side, typically byFowler-Nordheim tunneling mechanism. As electrons are transferred fromthe floating gate to the p-well region, the threshold voltage of aselected cell is lowered. Erasing can be performed on the entire memoryarray, on individual blocks, or another unit of cells. In oneembodiment, after erasing the memory cells, all of the erased memorycells will be in state S0 (see FIG. 6).

At step 554, soft programming is performed to narrow the distribution oferased threshold voltages for the erased memory cells. Some memory cellsmay be in a deeper erased state than necessary as a result of the eraseprocess. Soft programming can apply programming pulses to move thethreshold voltage of the deeper erased memory cells closer to the eraseverify level. For example, looking at FIG. 6, step 554 can includetightening the threshold voltage distribution associated with state S0.In step 556, the memory cells of the block are programmed as describedherein. The process of FIG. 9 can be performed at the direction of thestate machine using the various circuits described above. In otherembodiments, the process of FIG. 9 can be performed at the direction ofthe controller using the various circuits described above. Afterperforming the process of FIG. 9, the memory cells of the block can beread.

FIG. 10 is a flow chart describing one embodiment of a process forperforming programming on memory cells connected to a common word line.The process of FIG. 10 can be performed one or multiple times duringstep 556 of FIG. 9. For example, the process of FIG. 10 can be used toperform the full sequence programming of FIG. 6, in which case theprocess of FIG. 10 would be performed once for each word line. In oneembodiment, the programming process is performed in an order that startsfrom the word line closest to the source line, working toward the bitline. The process of FIG. 10 can also be used to perform the programmingof a page of data for a word line, with respect to the programmingprocess of FIGS. 7A-I, in which case the process of FIG. 10 would beperformed three times for each word line. Other arrangements can also beused. The process of FIG. 10 is performed at the direction of the statemachine 222.

Typically, the program voltage applied to the control gate during aprogram operation is applied as a series of program pulses. In betweenprogramming pulses are a set of verify pulses to enable verification. Inmany implementations, the magnitude of the program pulses is increasedwith each successive pulse by a predetermined step size. In step 608 ofFIG. 10, the programming voltage (Vpgm) is initialized to the startingmagnitude (e.g., ˜12-16V or another suitable level) and a programcounter PC maintained by state machine 222 is initialized at 1. In step610, a program pulse of the program signal Vpgm is applied to theselected word line (the word line selected for programming). Theunselected word lines receive one or more boosting voltages (e.g., ˜9volts) to perform boosting schemes known in the art. If a memory cellshould be programmed, then the corresponding bit line is grounded. Onthe other hand, if the memory cell should remain at its currentthreshold voltage, then the corresponding bit line is connected toV_(DD) to inhibit programming. More information about boosting schemescan be found in U.S. Pat. No. 6,859,397 and U.S. patent application Ser.No. 11/555,850, both of which are incorporated herein by reference.

In step 610, the program pulse is concurrently applied to all memorycells connected to the selected word line so that all of the memorycells connected to the selected word line are programmed together. Thatis, they are programmed at the same time (or during overlapping times).In this manner all of the memory cells connected to the selected wordline will concurrently have their threshold voltage change, unless theyhave been locked out from programming.

In step 612, the states of the selected memory cells are verified usingthe appropriate set of target levels. Step 612 of FIG. 10 includesperforming one or more verify operations. In general, during verifyoperations and read operations, the selected word line is connected to avoltage, a level of which is specified for each read and verifyoperation (e.g. see B, C, D, E, F, G and H of FIG. 7I) in order todetermine whether a threshold voltage of the concerned memory cell hasreached such level. After applying the word line voltage, the conductioncurrent of the memory cell is measured to determine whether the memorycell turned on in response to the voltage applied to the word line. Ifthe conduction current is measured to be greater than a certain value,then it is assumed that the memory cell turned on and the voltageapplied to the word line is greater than the threshold voltage of thememory cell. If the conduction current is not measured to be greaterthan the certain value, then it is assumed that the memory cell did notturn on and the voltage applied to the word line is not greater than thethreshold voltage of the memory cell.

There are many ways to measure the conduction current of a memory cellduring a read or verify operation. In one example, the conductioncurrent of a memory cell is measured by the rate it discharges orcharges a dedicated capacitor in the sense amplifier. In anotherexample, the conduction current of the selected memory cell allows (orfails to allow) the NAND string that included the memory cell todischarge the corresponding bit line. The voltage on the bit line ismeasured after a period of time to see whether it has been discharged ornot. Note that the technology described herein can be used withdifferent methods known in the art for verifying/reading. Moreinformation about verifying/reading can be found in the following patentdocuments that are incorporated herein by reference in their entirety:(1) United States Patent Application Pub. No. 2004/0057287,“Non-Volatile Memory And Method With Reduced Source Line Bias Errors,”published on Mar. 25, 2004; (2) United States Patent Application Pub No.2004/0109357, “Non-Volatile Memory And Method with Improved Sensing,”published on Jun. 10, 2004; (3) U.S. Patent Application Pub. No.20050169082; and (4) U.S. Patent Publication 2006/0221692, titled“Compensating for Coupling During Read Operations of Non-VolatileMemory,” Inventor Jian Chen, filed on Apr. 5, 2005.

If it is detected that the threshold voltage of a selected memory cellhas reached the appropriate target level, then the memory cell is lockedout of further programming by, for example, raising its bit line voltageto Vdd during subsequent programming pulses. Additionally, a passvoltage (e.g. ˜10 volts) is applied to the unselected word lines duringa programming operation (e.g., step 610). The unselected word lines (atthe pass voltage) couple to the unselected bit lines (at Vdd), causing avoltage (e.g. approximately eight volts) to exist in the channel of theunselected bit lines, which prevents programming. Other schemes forlocking out memory cells from programming can also be used with thetechnology described herein.

Looking back at FIG. 10, in step 614 it is checked whether all of memorycells have reached their target threshold voltages. If so, theprogramming process is complete and successful because all selectedmemory cells were programmed and verified to their target states. Astatus of “PASS” is reported in step 616. Note that in someimplementations, in step 614 it is checked whether at least apredetermined number of memory cells have been properly programmed. Thispredetermined number can be less than the number of all memory cells,thereby allowing the programming process to stop before all memory cellshave reached their appropriate verify levels. The memory cells that arenot successfully programmed can be corrected using error correctionduring the read process.

If, in step 614, it is determined that not all of the memory cells havereached their target threshold voltages, then the programming processcontinues. In step 618, the program counter PC is checked against aprogram limit value (PL). One example of a program limit value is 20;however, other values can be used. If the program counter PC is not lessthan the program limit value, then it is determined in step 630 whetherthe number of memory cells that have not been successfully programmed isequal to or less than a predetermined number. If the number ofunsuccessfully programmed memory cells is equal to or less than thepredetermined number, then the programming process is flagged as passedand a status of PASS is reported in step 632. In many cases, the memorycells that are not successfully programmed can be corrected using errorcorrection during the read process. If however, the number ofunsuccessfully programmed memory cells is greater than the predeterminednumber, the program process is flagged as failed and a status of FAIL isreported in step 634.

If, in step 618, it is determined that the Program Counter PC is lessthan the Program Limit value PL, then the process continues at step 620during which time the Program Counter PC is incremented by 1 and theprogram voltage Vpgm is stepped up to the next magnitude. For example,the next pulse will have a magnitude greater than the previous pulse bya step size (e.g., a step size of 0.1-0.4 volts). In step 622, it isdetermined whether a trigger has occurred. In one embodiment, a triggerhas occurred when the magnitude of the program voltage Vpgm (e.g., aprogram pulse) reaches a trigger voltage. Other embodiments could useother triggers (e.g., based on time, number of bits programmed, numberof pulses, current, etc.). If the trigger has not occurred, the processloops back to step 610 and the next program pulse (at the new magnitudeset in step 620) is applied to the selected word line so thatprogramming on all bit lines (except those memory cells locked-outbecause they reached their target state) occurs. The process continuesfrom step 610 as described above.

The trigger is set so that it signals or otherwise indicates a lock-outcondition that involves capacitive coupling. In general, there iscapacitive coupling between neighboring floating gates. When bothneighboring floating gates (first floating gate and second floatinggate) are being programmed, the capacitive coupling remains constantand/or predictable. When the first floating gate locks-out fromprogramming because it reaches its target state, the voltage potentialof that first floating gate will increase because of boosting. Becausethe first floating gate has the higher voltage potential, capacitivecoupling to the second floating gate increases. The higher capacitivecoupling will increase the voltage on the second floating gate, whichwill increase the speed of programming of the second floating gate. Thiscan cause over-programming. The risk over over-programming is greater atthe transition from the slower programming (when both neighbor memorycells are still being programmed) to the faster programming (when amemory cell is being programmed and its neighbor memory cell isinhibited from programming).

FIG. 11A shows two neighboring floating gates 806 and 810. Each floatinggate 806 and 810 is positioned above respective active areas 804 and808. A common word line polysilicon layer 802 acts as control gates forboth floating gates and also provides a shield 805 between the floatinggates. Shield 805 reduces coupling between floating gates 806 and 810.FIG. 11A shows both floating gates being programmed; therefore, theiractive areas are set at zero volts. As described above, if one of thefloating gates is locked-out from programming, its active area will beboosted up to between 7 and 10 volts, thereby boosting the voltagepotential of the respective floating gate and causing increasedcapacitive coupling to its neighbor floating gate. The neighbor floatinggate will then program faster. Faster programming could causeover-programming.

Although shield 805 between the floating gates 806 and 810 helps toreduce the capacitive coupling, when a large voltage is applied to theword line the polysilicon shield 805 becomes depleted. For example, FIG.11B shows the same two floating gates 806 and 810 with a dotted line 812in the word line polysilicon layer 802. The area below dotted line 812is depleted. Because the area below dotted line 812 is depleted, it doesnot provide full shielding to the capacitive coupling described above.

FIG. 11C shows the same two floating gates 806 and 810 with the depletedregion below dotted line 812. However, FIG. 11C shows floating gate 806being locked-out from programming. Therefore, active area 804 is at ahigh voltage which causes floating gate 806 to be at a high voltage.Because floating gate 806 is at a higher voltage and shield 805 isdepleted, the capacitive coupling between floating gates 806 and 810will cause floating gate 810 to have a higher potential and, therefore,program faster.

In one embodiment device characterization (including simulation) is usedto determine at what word line voltage the polysilicon word line layer802 becomes depleted so that coupling occurs, as described with respectto FIG. 11C. In other embodiments, this word line voltage can bemeasured by testing actual silicon. In some embodiments, every piece ofsilicon can be tested. In other embodiments, a sample of parts can betested and the measured voltage can be used on an entire group of parts.Other means for determining the voltage that starts depletion can alsobe used.

That word line voltage in which the depletion is severe enough to causeincrease in programming speed as described above is the trigger voltageused in step 622 of FIG. 10. Thus, if the magnitude of the Vpgm programpulse has reached the trigger voltage for which there is sufficientdepletion in the word line polysilicon layer to allow coupling, then thetrigger is met and the process proceeds to step 624 of FIG. 10. Thecondition at which the word line polysilicon layer is depleted andallows coupling when one neighbor is locked-out and the other neighboris still programming, thereby potentially speeding up the programming,is referred to herein as the lock-out condition.

If the trigger has been met in step 622, it is determined whether thechance of additional lock-out conditions is low in step 624. Asdiscussed above, a lock-out condition occurs when one memory cell isbeing programmed, a neighbor memory cell is locked-out from programming,and the word line voltage is high enough. A lockout condition causesfaster programming. Over-programming can occur when there is atransition from slower programming to faster programming. Thus, in oneembodiment, the system checks to see if there are potential transitionsfrom slow to fast programming that can occur due to onset of the lockoutcondition. The system checks for potential transitions from slow to fastprogramming by checking the potential number of new/additional lock-outconditions. In some embodiments, the system can tolerate a small numberof errors because these errors can be corrected during the read processusing error correction schemes known in the art. Therefore, if thenumber of potential lock-out conditions is small enough, the system cantolerate the potential for error and not have to correct for it duringprogramming. In those cases where the chance of new the lock-outcondition is low for the current programming process depicted in FIG.10, then the process continues from step 624 back to step 610, and thenext program pulse is applied in order to program memory cells on allbit lines that have not been locked-out from programming. If, in step624, it is determined that the potential number of new/additionallock-out conditions is not low, then the process proceeds to performsteps 626 and 628 which includes programming memory cells on even bitlines separately and at a different time than programming memory cellson odd bit lines.

Looking back at FIG. 4, a block of memory cells is depicted (block i).In one embodiment, the memory cells along a word line are broken up intotwo groups. The first group are all those memory cells connected to oddbit lines (e.g., BL1, BL3, BL5, . . .). The second group includes allmemory cells connected to even bit lines (e.g., BL0, BL2, BL4, . . . ).As can be seen from FIG. 4, the even bit lines and odd bit lines areinterleaved. Thus, the group of memory cells connected to the even bitlines are interleaved with the memory cells connected to the odd bitlines. If only even bit lines are being programmed, then all of thememory cells connected to the odd bit lines would be locked-out. Thiswould guarantee a situation where any memory cell being programmed wouldhave both its neighbors locked-out. Although this could cause coupling,since it is guaranteed that both neighbors are locked-out, the couplingis predictable and constant. As a result, over-programming is notlikely. The memory cells connected to a word line can be divided intomore than two groups and can be divided into types of groups other thanodd and even groups.

In step 626 of FIG. 10, a program pulse is applied to the selected wordline in order to program only those memory cells connected to even bitlines. Thus, the even bit lines will be at zero volts while the odd bitlines will have Vdd applied. During step 626, only even bit lines willbe programmed. After step 626 is performed, step 628 is performed, whichincludes applying a program pulse to the same selected word line. Duringstep 628, only memory cells connected to odd bit lines will beprogrammed. Thus, step 628 will include applying zero volts to odd bitlines and Vdd to even bit lines. Thus, steps 626 and 628 includeapplying two successive program pulses to the same word line (and, thus,to the same set of memory cells connected to that word line); however,only even memory cells are programmed during the first pulse (step 626)and only odd memory cells are programmed during the second pulse (step628). Therefore, memory cells connected to even bit lines (even memorycells) are programmed separately from memory cells connected to odd bitlines (odd memory cells). For example, if WL2_i is the selected wordline (see FIG. 4), then memory cells connected to BL0, BL2, BL4 andWL2_i will be programmed in step 626 and memory cells connected to BL1,BL3, BL5 and WL2_i will be programmed in step 628. Although the oddmemory cells receive the program pulse of step 626, they are inhibitedfrom programming during step 626. Although the even memory cells receiveprogram pulses during step 628, they are inhibited from programmingduring step 628. After step 628, the process loops back to step 612 andmemory cells on even bit lines and odd bit lines are all verifiedtogether (unless, in some implementations, they have previously beenlocked out because they reached their target). The process continuesfrom step 612, as described above. There is no verify operationperformed between steps 626 and 628.

FIG. 12 is an example waveform for the program voltage Vpgm. The signalof FIG. 12 includes pulses 702, 704, 706, 708, 710, 712, 714, 716, 718,720, 722, 724, 726, 728, 730, 732, 734 and 736. Program pulses 702-720are all applied prior to the trigger. Each of the magnitudes of thosepulses are less than the trigger voltage. Pulses 702-720 are applied aspart of iterations of step 610 of FIG. 10. After applying pulse 720, thetrigger voltage has been reached (e.g., the magnitude of Vpgm is greaterthan the trigger voltage) and the process performs the programming ofeven bit lines separately from odd bit lines (step 626 and step 628).Therefore, FIG. 12 shows two pulses at 722 and 724. Programming pulse722 is for programming memory cells connected to even bit lines (step626) and program pulse 724 is for programming memory cells connected toodd bit lines (step 724); however, both pulses 722 and 724 are bothapplied to the same selected word line. In the example of FIG. 12, theprocess continues programming odd and even bit lines separately (firstprogramming even bit lines and subsequently programming odd bit lines).For example, pulses 726 and 728 are the next iteration of steps 626 and628 of FIG. 10. Pulses 730 and 732 are a subsequent iteration of steps626 and 628. Pulses 734 and 736 are the final iteration of steps 626 and628 in the example of FIG. 12. After applying pulses 734 and 736, allmemory cells have appropriately verified (or enough memory cells haveverified) so that the process is successfully completed.

FIG. 13 provides another example waveform for the programming pulse ofVpgm. The example of FIG. 13 includes the programming processtransitioning from all bit line programming (step 610) to separateprogramming for even and odd bit lines (steps 626 and 628), and thentransitioning back to all bit line programming. Programming pulses 750,752, 754, 756, 758, 760, 762, 764, 766 and 768 are applied duringiterations of step 610. After programming pulse 768, the trigger voltagehas been reached and the process performs steps 626 and 628 to programmemory cells connected to even bit lines with programming pulse 770 andmemory cells connected to odd bit lines with programming pulse 772. FIG.13 shows three iterations of steps 626 and 628. In the second iterationof steps 626 and 628, programming pulse 774 is used to program memorycells connected to even bit lines and program pulse 776 is used toprogram memory cells connected to odd bit lines. In the third iterationof steps 626 and 628, programming pulse 778 is used to program memorycells connected to even bit lines and programming pulse 780 is used toprogram memory cells connected to odd bit lines. After applyingprogramming pulse 780 in step 628, it is determined that the incidenceof lock-out condition is low. Therefore, after step 624 the processcontinues at step 610 and a programming pulse 782 is applied to programmemory cells connected to all bit lines (except those memory cells thathave been locked-out because they have reached their target state). Thenext iteration of the process of FIG. 10 would include applying oneprogramming pulse 784 in step 610. After applying programming pulse 784,it is determined that enough memory cells have verified and theprogramming process has completed successfully.

As described above, a set of verify operations are performed betweenprogramming pulses. In one embodiment, a verify pulse is applied to theselected word line for each verify operation. For example, if there areeight potential data states that memory cells can be in, then there willbe seven verify operations and, therefore, seven verify pulses. FIG. 14shows an example of programming pulses 706, 708 and 710 (see also FIG.12) and the verify pulses that are applied between the programmingpulses 706, 708 and 710. Each verify pulse of FIG. 14 is associated witha verify operation, as described above.

FIG. 15 also shows programming pulses with verify pulses in between.FIG. 15 shows programming pulses 722, 724, 726, 728, 730 and 732 of FIG.12. These six programming pulses are associated with applyingprogramming pulses after the trigger voltage has been reached.Therefore, odd and even memory cells are programmed separately. Asdiscussed above, programming pulse 722 programs memory cells connectedto even bit lines while programming pulse 724 programs memory cellsconnected to odd bit lines. In one embodiment, there are no verifyoperations between programming pulses 722 and 724. Subsequent to programpulse 724 and prior to the next pair of pulses 726, 728, a set of verifypulses are applied in order to perform verify operations. Between pulses726 and 728, there are no verify operations performed. Subsequent topulse 728 and prior to the next pair of pulses (730, 732), a set ofverify pulses are applied in order to perform a corresponding set ofverify operations.

FIG. 16 depicts the behavior various signals during programming. Morespecifically, Figure shows the operation during one iteration of steps610, 626 or 628 of FIG. 10. The depicted program operation can begrouped into a Bit Lines Pre-charge Phase, a Program Phase and aDischarge Phase.

During period (1) of the Bit Lines Pre-charge Phase, the source selecttransistor is turned off by maintaining SGS at 0V while the drain selecttransistor is turned on by SGD going high to VSG, thereby allowing a bitline to access a NAND string. During period (2) of the Bit LinesPre-charge Phase. the bit line voltage of a program-inhibited NANDstring (BL inhibit) is allowed to rise to a predetermined voltage givenby VDD. When the bit line voltage of the program-inhibited NAND stringrises to VDD, the program-inhibited NAND string will float when the gatevoltage SGD on the drain select transistor drops to VDD in period (3).The bit line voltage of a programming NAND string (BL pgm) is activelypulled down to 0V. In some alternative embodiments, the bit line voltageof the programming NAND string is biased based on whether one or both ofits neighbors is in program-inhibit mode or not. More information aboutthis bias can be found in U.S. Pat. No. 7,187,585, incorporated hereinby reference in its entirety.

During period (4) of the Program Phase, the unselected word lines(WL_unsel) are set to VPASS to enable boosting of the NAND string. Sincea program-inhibited NAND string is floating, the high VPASS applied tothe control gates of the unaddressed memory transistors boost up thevoltages of their channels and charge storage elements, therebyinhibiting programming. VPASS is typically set to some intermediatevoltage (e.g., ˜10V) relative to Vpgm (e.g., ˜12-24V).

During period (5) of the Program Phase, the programming voltage Vpgm isapplied to the selected word line (WL_sel) as a programming pulse. Theprogramming pulse of period (5) corresponds to any of the pulses 702-736of FIG. 12 or pulses 750-784 of FIG. 13. The memory cells beinginhibited (i.e., with boosted channels and charge storage units) willnot be programmed. The selected memory cells (connected to the selectedword line) will be programmed During period (6) of the Discharge Phase,the various control lines and bit lines are allowed to discharge.

FIG. 17 is a flow chart describing one embodiment of a process fordetermining whether the chance of additional lock-out conditions is low(see step 624 of FIG. 10). In step 850, each memory cell is compared toits neighboring memory cell along the same word line. In step 852, thesystem counts the number X of potential transitions into lock-outcondition. A potential lockout condition exists if two neighbor memorycells are both still being programmed because one of the neighbors canpotentially reach its target before the other and lockout. Thus, in oneembodiment, step 852 includes counting the number of pairs ofneighboring memory cells that are still being programmed. If the numberof potential lockout conditions is greater than a threshold (step 854),then the chance of additional lock-out conditions is not low (step 858).If the number of potential lockout conditions is not greater than athreshold, then the chance of additional lock-out conditions is low(step 856). The threshold of step 854 is set based on the number of bitsthat can be corrected by error correction codes. For example, oneembodiment includes an error correction code that can fix up to sevenbits of incorrect data (amounting to approximately 0.01 percent of thedata). Thus, if the number of potential lockout conditions is less thanseven, then the chance of additional lock-out conditions is low (step856). Other thresholds can also be used. In another embodiment, step 850would include only a subset of memory cells being compared to theirneighbors, and the results would be extrapolated for the entirepopulation and compared to the threshold.

FIG. 18 is a block diagram of one example of hardware that can implementthe process of FIG. 17. Data latches 494 (see FIG. 5) for all the memorycells provide data to shift register 880. In one embodiment, shiftregister 880 can include the actual data latches 494. Shift register 880includes all the data for all of the bit lines. The data is shifted outone bit at a time, first into one bit register 882 and then into one bitregister 884. The data in register 882 and the data from register 884are sent to NOR gate 886. The output of NOR gate 886 is sent toaccumulator 888. The output of accumulator 888 is provided to statemachine 222, which determines whether the number of potential lockoutconditions is not greater than a threshold. The circuit of FIG. 18counts the incidences where neighboring bit lines store 0-0. In oneexample, to configure the sense circuitry to apply the appropriatevoltage on the bit line, a data latch is used to store an indication ofwhether the particular memory cell should be programmed or inhibitedfrom programming. In one embodiment, the respective data latch willstore one (1) if the bit line is to be inhibited and will store zero (0)if the bit line is to be set up for programming. Opposite polarities canalso be used. Thus, the circuit of FIG. 18 will look for neighboring bitlines where the data are 0-0 and count the number of times that happensusing accumulator 888. If the number of times that the accumulator 888counts 0-0 is greater than the threshold, then the state machineconcludes that the chance of additional lock-out conditions is not low(and, in FIG. 10, the process would continue at step 626).

FIG. 19 describes another embodiment of determining whether the chanceof additional lock-out conditions is low. In step 902, the number ofmemory cells that are still being programmed are counted. In analternative, the number of memory cells that are locked out are counted.In step 904, it is determined whether the number of memory cells stillbeing programmed is less than a threshold. If the number of memory cellsstill being programmed is less than the threshold (step 904), then thechance of additional lock-out conditions is low (step 906). If thenumber of memory cells being locked-out is not less than the threshold,then the chance of additional lock-out conditions is not low (step 908).In one embodiment, the threshold could be set so that if only 0.4% ofthe memory cells are still being programmed (or 99.6% are locked out)then the chance of additional lock-out conditions is low. Otherthresholds can also be used.

FIG. 20 is a block diagram depicting one example of hardware that can beused to implement the process of FIG. 19. FIG. 20 shows each of theprocessors 492 for each of the groups of bit lines (e.g., one processor492 for 8 bit lines) in communication with a comparator circuit 920.Each of the processors will indicate whether their respective bit linesare being programmed or locked-out. Comparator 920 includes a circuitfor counting the number of bit lines that are locked out. In oneembodiment, this can be accomplished by providing the data from thelatches discussed above. Comparator 920 can access a parameter 922 whichindicates the threshold (see step 904) and compare that threshold to thesum of bit lines locked out. The output of comparator 920 is sent tostate machine 222.

Looking back at FIG. 10, a trigger is used (step 622) to change theprogramming process from programming odd and even memory cells togetherto programming odd and even memory cells separately. One embodimentincludes using device characterization (including simulation) todetermine an appropriate trigger voltage. In some embodiments, thetrigger voltage can be trimmed separately for each integrated circuit.That is, subsequent to manufacturing the integrated circuits, eachintegrated circuit can be tested. Based on that test, the triggervoltage can be set or adjusted.

FIGS. 21, 22 and 23 are flow charts describing three embodiments fortrimming or setting the trigger value. The processes of FIGS. 21-23 canbe performed on one block. The data from that one block can then be usedfor all the blocks on that memory device. In one alternative, multipleblocks can be tested and the results applied to all blocks. In anotheralternative embodiment, the processes of FIG. 21-23 can be performed onevery block and each block will then have its own trigger value. In oneembodiment, only one word line is tested in a block. In otherembodiments, more than one word line can be tested and the resultsaveraged or otherwise combined. In other implementations, other units(e.g., word line, groups of word lines, page, sector, etc.) can beselected for testing.

In step 1002 of FIG. 21, the particular block (or blocks) under test iserased. The process will then program the even cells on one selectedword line. In one embodiment, only one word line will receiveprogramming. Based on that one word line, a new trigger value will bedetermined for the entire block, entire chip, or the entire memorysystem. In other embodiments, multiple word lines can be programmed andthe data can be averaged or each word line can have its own triggervalue. In step 1004, memory cells connected to the selected word lineare programmed. The programming process of step 1004 includes all of thememory cells connected to the odd bit lines and even bit lines beenabled for programming and applying programming pulses with increasingmagnitude until the programming pulses reach a magnitude of Vpgm_test.In one embodiment, the Vpgm_test is initially set at two volts below thetrigger voltage determined from device characterization. The programmingprocess of step 1004 is similar to the process of FIG. 10 with theexception that after step 620, the process always loops back to step 610(there is no step 622-628). After the programming process of step 1004is complete, then the top and bottom of the threshold voltagedistribution for the memory cells connected to even bit lines aremeasured in step 1006. In step 1008, the block is erased.

In step 1010, the memory cells connected to the even bit lines are againprogrammed; however, the memory cells connected to the odd bit lines areinhibited from programming for all of the programming pulses of step1010. Step 1010 includes applying a series of programming pulses withincreasing magnitude until the magnitude of a program pulse is equal tothe same Vpgm_test as step 1004. In step 1012, the threshold voltagedistribution to the memory cells connected to the even bit lines ismeasured. In step 1014, the top and bottom of the threshold voltagedistributions measured in steps 1012 and 1006 are compared. In oneembodiment, the lower bounds of the two threshold voltage distributionsare compared. In another embodiment, the upper bounds of each thresholdvoltage distribution are compared. If the difference between the lowerbounds (or upper bounds) of the threshold voltage distributions is notgreater than a threshold, then Vpgm_test is increased by a predeterminedamount (e.g., 0.5 volts or other value) and the process repeats bylooping back to step 1002. If the difference between the lowest pointsof the two threshold voltage distributions is greater than a threshold,then the trigger voltage (from the value determined by devicecharacterization) is modified to become the current value of Vpgm_testin step 1020. In some embodiments, Vpgm_test can be further modified byadding some margining offset to account for consideration that thesample size may not capture the actual worst case. In one embodiment,the threshold of step 1016 is equal to 0.5 volts and the program pulsestep size used for programming in steps 1004 and 1010 is 0.4 volts.

FIG. 22 provides another embodiment of a process for determining ortrimming the trigger voltage. In step 1050, the block underconsideration is erased. With the memory cells connected to the odd bitlines selected for programming in each iteration of the programmingprocess, the memory cells connected to the even bit lines are programmeduntil their threshold voltage reaches a target level of Vx volts in step1052. Vx can be set by experimentation. One example value of Vx is 3.5volts. In step 1054, the number of programming pulses needed to properlyprogram the memory cells connected to even bit lines during step 2052 isrecorded. In step 1056, the block under consideration is erased. In step1058, the memory cells connected to even bit lines are programmed againuntil their threshold voltage has reached Vx volts. In step 1058, thememory cells connected to the odd bit lines are always inhibited foreach cycle. In step 1060, the number of program pulses needed to programthe memory cells in step 1058 is recorded. In step 1062, the number ofpulses for each of the tests (steps 1054 and 1060) are compared. It ispredicted that the number of pulses measured in step 1060 will be fewerthan the number of pulses measured in step 1054. This difference innumber of pulses indicates a magnitude of the interference effectassociated with the lock-out condition described above. If thedifference is greater than a threshold, then the trigger voltage is setto the magnitude of the last pulse from the programming process of step1058. If the difference is not greater than the threshold, then thevoltage VX is increased (e.g., by 0.5 volts) and the process loops backto step 1050 to repeat the tests. In one example, the threshold of step1064 is equal to one pulse. Other thresholds can also be used.

FIG. 23 is another embodiment for determining or trimming the triggervoltage. In step 1102, the selected block or blocks are erased. In step1104, the memory cells connected to even bit lines are programmed untiltheir threshold voltage is equal to a voltage Vy. During the programmingprocess of step 1104, the memory cells connected to the odd bit linesare always selected for programming. In step 1106, the number of memorycells connected to even bit lines that are over-programmed are measured.For example, an ideal threshold voltage distribution can be estimatedbased on simulation and an upper level can be determined for that idealthreshold voltage distribution. If the threshold voltage of a memorycell exceeds an upper limit of that ideal distribution, that memory cellis over programmed. For example, looking at FIG. 7I, state S6 has alower bound G and an upper bound OP. If a memory cell has a thresholdvoltage greater than OP, then that memory cell is over-programmed. Inother embodiments, the compare level for over-programming could bedifferent.

Looking back at FIG. 23, in step 1108, one more programming pulse isapplied to the selected word line. While that programming pulse is beingapplied at step 1108, all memory cells connected to odd bit lines areinhibited from programming. Those memory cells that reached thresholdvoltage of Vy in step 1104 will remain locked-out during step 1108.Thus, the programming pulse of step 1108 will only program those memorycells which had not already reached a threshold voltage of Vy. In step1110, the number of over-programmed memory cells is again measured. Instep 1112, the number of over-programmed cells measured in step 1110 iscompared to the number of over-programmed memory cells measured in step1106. If the difference in the number of over-programmed memory cells isgreater than a threshold, then the trigger voltage is set to themagnitude of the pulse applied in step 1108. One example of a thresholdfrom step 1114 is five memory cells. If the difference is not greaterthan the threshold (step 1114), then the voltage level of Vy isincreased (e.g., by 0.5 volts) at step 1116 and the process loops backto step 1102 and repeats.

In some embodiments, a non-volatile storage system can make dynamicadjustments to the triggering voltage in order to account for changesdue to environmental or usage conditions, such as cycling history,temperature, etc. FIG. 24 is a flow chart describing one embodiment fordynamically changing the trigger voltage based on the number ofprogram/erase cycles. A program/erase cycle includes performing an eraseprocess and a program process. As the non-volatile storage systemperforms many programming/erase cycles, charge may get trapped in thedielectric region between the floating gate and the channel. Thiscondition may decrease the depletion region discussed above with respectto FIGS. 11A-C. Therefore, as the device becomes cycled many times, itmay be possible to increase the trigger voltage so that the separateprogramming of odd and even memory cells happens later in theprogramming process. In step 1240 of FIG. 24, the memory device performsX program/erase cycles. In one example, X program cycles could be 10,000program/erase cycles. Other values for X could also be used. Afterperforming X program/erase cycles, the trigger voltage is raised (e.g.,by 0.5 volts) in step 1242. After raising the trigger voltage in step1242, the memory system will perform Y program/erase cycles in step1244. In one example, Y program/erase cycles could be 5,000program/erase cycles. In step 1246, the trigger voltage will again beraised (e.g., by 0.2 volts). After raising the trigger voltage in step1246, the memory system will continue performing program/erase cycles(step 1248). FIG. 24 shows the memory device raising the trigger voltagetwice. However, in other embodiments, the trigger voltage can be raisedonly once or more times than twice. Different values of X and Y can bedetermined based on device characterization or experimental means.

FIG. 25 is a block diagram of one example of components used to performthe process of FIG. 24. FIG. 25 shows state machine 222 in communicationwith register 1282 storing a trigger parameter and register 1284 storinga cycle parameter. Compensation circuit 1286 is also in communicationwith register 1282 and register 1284. The trigger parameter is anindication of the trigger voltage (or other trigger). The triggerparameter can be an identification of a voltage magnitude, a pulsenumber, or something else. The cycle parameter can indicate the numberor program/erase cycles that have been performed. Based on the value ofthe cycle parameter, the compensation circuit will update the triggerparameter, when appropriate. For example, compensation circuit 1286 mayupdate the trigger parameter as part of step 1242 and 1246 of FIG. 24.State machine 222 will use the trigger parameter during step 622 of FIG.10.

FIG. 26 is a flow chart describing an embodiment for dynamicallyadjusting the trigger voltage based on temperature. In step 1302, thememory system will measure the temperature. In one embodiment, thememory system can include a temperature sensor. Based on the measuredtemperature, the trigger voltage can be adjusted in step 1304. It isanticipated that the depletion region should be worse at coldtemperatures so the trigger should happen earlier in the programprocess. This can be done by lowering the trigger voltage when there isa cold temperature. If the temperature measured in step 1302 is colderthan a preset number, the trigger voltage can be lowered. If thetemperature measured in step 1302 is higher than the preset number, thenthe trigger voltage can be raised. In another embodiment, state machine222 can store a table which associates ranges of temperature withtrigger voltages. In step 1302, state machine 222 will read thetemperature and in step 1304, state machine 222 will look up a triggervalue in a table using the temperature as a key to the table. Thetrigger voltage found in the table will be stored in a parameter for useduring the programming process. In another embodiment, a compensationcircuit will read the measured temperature and adjust the triggervoltage in step 1304. In step 1306, the system will perform programmingusing the trigger voltage set in step 1304. After a certain amount ofperforming programming, the process will loop back to step 1302, thetemperature will be measured again and the trigger value can beoptionally adjusted in step 1304. In one embodiment, the loop of steps1302-1306 can be performed for every programming process. In alternativeembodiments, the process can be performed every N cycles or every N timeperiods, etc.

FIG. 27 is a block diagram depicting one example of components that canimplement the process of FIG. 26. FIG. 27 shows state machine 222 incommunication with register 1350 storing a trigger parameter. Thetrigger parameter is an indication of the trigger voltage (or othertrigger). The trigger parameter can be an identification of a voltagemagnitude, a pulse number, or something else. Compensation circuit 1352is in communication with register 1350 and temperature sensor 1354.Temperature sensor 1354 outputs a signal (voltage or current) indicativeof temperature. Based on the output of temperature sensor 1354,compensation circuit 1352 will update the trigger parameter. Forexample, compensation circuit 1352 may update the trigger parameter aspart of step 1304 of FIG. 26. The update of the trigger parameter may beperformed continuously, periodically, or on demand.

The foregoing detailed description of the invention has been presentedfor purposes of illustration and description. It is not intended to beexhaustive or to limit the invention to the precise form disclosed. Manymodifications and variations are possible in light of the aboveteaching. The described embodiments were chosen in order to best explainthe principles of the invention and its practical application, tothereby enable others skilled in the art to best utilize the inventionin various embodiments and with various modifications as are suited tothe particular use contemplated. It is intended that the scope of theinvention be defined by the claims appended hereto.

What is claimed is:
 1. A method for programming non-volatile storage,comprising: performing a first phase of an iterative programmingprocess, the first phase includes programming a first group ofnon-volatile storage elements together with a second group ofnon-volatile storage elements, the iterative programming processincludes alternately applying programming and verify pulses to at leasta portion of the first group of non-volatile storage elements and thesecond group of non-volatile storage elements, each non-volatile storageelement of the first group of non-volatile storage elements is incommunication with a different even control line of one or more evencontrol lines, each non-volatile storage element of the second group ofnon-volatile storage elements is in communication with a different oddcontrol line of one or more odd control lines, the one or more evencontrol lines and the one or more odd control lines are arranged in aninterleaving manner; detecting a first condition; and performing asecond phase of the iterative programming process, the second phaseincludes programming the first group of non-volatile storage elementsseparate from the second group of non-volatile storage elements, thesecond phase is performed subsequent to the first phase, the secondphase is performed in response to the detecting a first condition.
 2. Amethod according to claim 1, further comprising: detecting a secondcondition; and performing a third phase of the iterative programmingprocess, the third phase includes programming the first group ofnon-volatile storage elements together with second group of non-volatilestorage elements, the third phase is performed subsequent to the secondphase, the third phase is performed in response to the detecting asecond condition.
 3. A method according to claim 1, further comprising:adjusting the first condition prior to the second phase.
 4. A methodaccording to claim 3, wherein: the adjusting includes increasing atrigger voltage after a particular number of program/erase cycles hasoccurred.
 5. A method according to claim 3, wherein: the adjustingincludes lowering a trigger voltage if a measured temperature is lowerthan a particular preset temperature.
 6. A method according to claim 1,wherein: the detecting a first condition includes determining how manyof the first group of non-volatile storage elements and the second groupof non-volatile storage elements are still being programmed and have aneighbor that is selected for programming.
 7. A method according toclaim 1, wherein: the detecting a first condition includes determiningwhether the magnitude of a program voltage has reached a first thresholdvoltage.
 8. A method according to claim 7, wherein: the first thresholdvoltage is a preset value, the preset value is determined by measuringthe voltage at which word line depletion allows substantial couplingbetween neighboring non-volatile storage elements.
 9. A method accordingto claim 1, wherein: the detecting a first condition includesdetermining whether the magnitude of a program voltage has reached afirst threshold voltage and whether the number of potential lock-outconditions is greater than a particular number.
 10. A method accordingto claim 1, wherein: the detecting a first condition includesdetermining the number of pairs of neighboring non-volatile storageelements that are being programmed at a particular time.
 11. A methodaccording to claim 10, wherein: the pairs of neighboring non-volatilestorage elements share a common control line.
 12. A method according toclaim 1, wherein: the detecting a first condition includes determiningthe number of non-volatile storage elements that are being programmed ata particular time.
 13. A method according to claim 1, wherein: thedetecting a first condition includes determining the number ofnon-volatile storage elements that are locked-out at a particular time.14. A non-volatile storage apparatus, comprising: a plurality ofnon-volatile storage elements including a first group of non-volatilestorage elements and a second group of non-volatile storage elements,each non-volatile storage element of the first group of non-volatilestorage elements is in communication with a different even control lineof one or more even control lines, each non-volatile storage element ofthe second group of non-volatile storage elements is in communicationwith a different odd control line of one or more odd control lines, theone or more even control lines and the one or more odd control lines arearranged in an interleaving manner; one or more condition detectioncircuits, the one or more condition detection circuits detect whether afirst condition has occurred; and one or more managing circuits incommunication with the plurality of non-volatile storage elements, theone or more managing circuits program the first group of non-volatilestorage elements separately from the second group of non-volatilestorage elements after and in response to detection of the firstcondition, the one or more managing circuits program the first group ofnon-volatile storage elements together with the second group ofnon-volatile storage elements prior to detection of the first condition.15. A non-volatile storage apparatus of claim 14, wherein: the firstcondition is dynamically adjusted prior to detection of the firstcondition.
 16. A non-volatile storage apparatus of claim 14, wherein:the one or more condition detection circuits compare a measuredtemperature to a particular preset temperature.
 17. A non-volatilestorage apparatus of claim 14, wherein: the one or more conditiondetection circuits determine whether the magnitude of a program voltagehas reached a first threshold and whether the number of potentiallock-out conditions is greater than a particular number.
 18. Anon-volatile storage apparatus of claim 14, wherein: the one or morecondition detection circuits determine the number of non-volatilestorage elements that are being programmed at a particular time.
 19. Anon-volatile storage apparatus of claim 14, wherein: the first group ofnon-volatile storage elements is connected to a first word line; thesecond group of non-volatile storage element is connected to the firstword line; and each non-volatile storage element of the first group ofnon-volatile storage elements is connected to a different even bit lineof one or more even bit lines, each non-volatile storage element of thesecond group of non-volatile storage elements is connected to adifferent odd bit line of one or more odd bit lines, the one or moreeven bit lines and the one or more odd bit lines are arranged in aninterleaving manner.
 20. A method for programming non-volatile storage,comprising: performing a first phase of an iterative programmingprocess, the first phase includes programming a first group ofnon-volatile storage elements separate from a second group ofnon-volatile storage elements, the iterative programming processincludes alternately applying programming and verify pulses to at leasta portion of the first group of non-volatile storage elements and thesecond group of non-volatile storage elements; adjusting a firstcondition; detecting the first condition subsequent to the step ofadjusting; and performing a second phase of the iterative programmingprocess, the second phase includes programming the first group ofnon-volatile storage elements together with the second group ofnon-volatile storage elements, the second phase is performed subsequentto the first phase, the second phase is performed in response to thedetecting.
 21. A method for programming non-volatile storage,comprising: performing a first phase of an iterative programmingprocess, the first phase includes programming a first group ofnon-volatile storage elements separate from a second group ofnon-volatile storage elements, the iterative programming processincludes alternately applying programming and verify pulses to at leasta portion of the first group of non-volatile storage elements and thesecond group of non-volatile storage elements; detecting a firstcondition, the detecting a first condition includes determining thenumber of pairs of neighboring non-volatile storage elements that arebeing programmed at a particular time, the pairs of neighboringnon-volatile storage elements share a common control line; andperforming a second phase of the iterative programming process, thesecond phase includes programming the first group of non-volatilestorage elements together with the second group of non-volatile storageelements, the second phase is performed subsequent to the first phase,the second phase is performed in response to the detecting a firstcondition.
 22. The method of claim 1, wherein: the first group ofnon-volatile storage elements comprises a three-dimensional array ofstorage elements.
 23. The method of claim 1, wherein: the first group ofnon-volatile storage elements comprises a three-dimensional array ofmemory cells.
 24. The method of claim 1, wherein: the first group ofnon-volatile storage elements is arranged in a three-dimensional memorystructure.
 25. The non-volatile storage apparatus of claim 14, wherein:the first group of non-volatile storage elements comprises athree-dimensional array of storage elements.
 26. The non-volatilestorage apparatus of claim 14, wherein: the first group of non-volatilestorage elements comprises a three-dimensional array of memory cells.27. The non-volatile storage apparatus of claim 14, wherein: the firstgroup of non-volatile storage elements is arranged in athree-dimensional memory structure.
 28. The method of claim 20, wherein:the first group of non-volatile storage elements comprises athree-dimensional array of storage elements.
 29. The method of claim 20,wherein: the first group of non-volatile storage elements comprises athree-dimensional array of memory cells.
 30. The method of claim 20,wherein: the first group of non-volatile storage elements is arranged ina three-dimensional memory structure.
 31. The method of claim 21,wherein: the first group of non-volatile storage elements comprises athree-dimensional array of storage elements.
 32. The method of claim 21,wherein: the first group of non-volatile storage elements comprises athree-dimensional array of memory cells.
 33. The method of claim 21,wherein: the first group of non-volatile storage elements is arranged ina three-dimensional memory structure.